Successive approximation analog/digital converter with reduced chip area

ABSTRACT

A successive approximation A/D converter includes first and second S/H and comparators sampling and holding first and second external analog input voltages simultaneously and comparing the held, first and second external analog input voltages with a reference voltage to output first and second signals having levels corresponding to resultant comparisons, and a reference voltage generator operative in response to the first and second signals to generate the reference voltage. The two S/H and comparators share the single reference voltage generator. A reduced chip area can be achieved.

RELATED APPLICATION

This application is a continuation of U.S. application Ser. No.10/895,090 filed on Jul. 21, 2004 is now a U.S. Pat. No. 6,919,837.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to successive approximationAnalog/Digital (A/D) converters and particularly to those converting aplurality of analog input voltages each to a digital signal.

2. Description of the Background Art

Conventionally, A/D converters for servo control and other similar,mechanical control have been implemented by successive approximation A/Dconverters. The successive approximation A/D converter samples and holdsan analog input voltage and then compares the held analog input voltagewith a plurality of reference voltages sequentially to convert analoginput voltage to a multibit digital signal, for example as described inJapanese Patent Laying-Open No. 08-149007.

Conventionally, simultaneously sampling a plurality of analog inputvoltages necessitates a plurality of successive approximation A/Dconverters, which disadvantageously contributes to an increased chiparea for the converters.

SUMMARY OF THE INVENTION

The present invention mainly contemplates a successive approximation A/Dconverter capable of sampling a plurality of analog input voltagessimultaneously, and requiring a reduced chip area.

The present invention provides a successive approximation A/D converterincluding: a plurality of comparators associated with a plurality ofanalog input voltages, respectively, to each sample and hold acorresponding one of the analog input voltages to compare a held analoginput voltage with a voltage of a comparison node to output a signalindicative of a resultant comparison; a control circuit causing theplurality of comparators to simultaneously sample and hold the pluralityof analog input voltages and subsequently select the plurality ofcomparators sequentially, one for a prescribed period of time, togenerate the digital signal as based on a signal output from a selectedone of the comparators; and a reference voltage generator operative inresponse to the signal output from the comparator selected by thecontrol circuit to control in voltage a comparison node of thecomparator selected. Thus a plurality of analog input voltages cansimultaneously be sampled and held. Furthermore, the plurality ofcomparators sharing a single reference voltage generator can contributeto a reduced chip area.

Furthermore, the present invention in another aspect provides asuccessive approximation A/D converter including: a plurality ofcomparators associated with a plurality of analog input voltages,respectively, to each sample and hold a corresponding one of the analoginput voltages to compare a held analog input voltage with a voltage ofa comparison node to output a signal indicative of a resultantcomparison; a control circuit causing the plurality of comparators tosample and hold the plurality of analog input voltages simultaneouslyand subsequently in response to a signal output from each comparatorgenerate the digital signal; a voltage generation circuit generating aplurality of different reference voltages; and a selector associatedwith each comparator and operative in response to a signal output from acorresponding one of the comparators to select one of the plurality ofreference voltages and provide a selected one of the reference voltagesto a comparison node of the corresponding one of the comparators.Furthermore, the plurality of comparators sharing a single voltagegeneration circuit can contribute to a reduced chip area.

The foregoing and other objects, features, aspects and advantages of thepresent invention will become more apparent from the following detaileddescription of the present invention when taken in conjunction with theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing a configuration of the presentsuccessive approximation A/D converter in a first embodiment.

FIG. 2 is a circuit block diagram showing a configuration of thereference voltage generator shown in FIG. 1.

FIGS. 3A and 3B are timing plots for illustrating the FIG. 1 successiveapproximation A/D converter in operation.

FIGS. 4A and 4B are timing plots for illustrating the first embodimentin an exemplary variation.

FIG. 5 is a circuit block diagram showing a configuration of the presentsuccessive approximation A/D converter in a second embodiment.

FIG. 6 is a block diagram showing a configuration of the presentsuccessive approximation A/D converter in a third embodiment.

FIG. 7 is a circuit block diagram showing a configuration of thereference voltage generator shown in FIG. 6.

FIGS. 8A and 8B are timing plots for illustrating the FIG. 6 successiveapproximation A/D converter in operation.

FIG. 9 is a circuit block diagram showing the third embodiment in anexemplary variation.

DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment

FIG. 1 is a block diagram showing a configuration of a successiveapproximation A/D converter 1 of the present invention in a firstembodiment. As shown in FIG. 1, successive approximation A/D converter 1includes sample and hold (S/H) and comparators 2 and 3, a successiveapproximation register (SAR) and control circuit 4, a decoder 5, and areference voltage generator 6.

S/H and comparator 2 is controlled by SAR and control circuit 4 tosample and hold an external analog input voltage VIA and compare inlevel the held analog input voltage VIA with a reference voltage VCreceived from reference voltage generator 6 and outputs to SAR andcontrol circuit 4 a signal φ2 having a level corresponding to a resultof the comparison.

S/H and comparator 3 is controlled by SAR and control circuit 4 tosample and hold an external analog input voltage VIB and compare inlevel the held analog input voltage VIB with reference voltage VCreceived from reference voltage generator 6 and outputs to SAR andcontrol circuit 4 a signal φ3 having a level corresponding to a resultof the comparison.

SAR and control circuit 4 is synchronized with an external clock signalCLK to operate to control S/H and comparators 2 and 3. Furthermore, SARand control circuit 4 is driven by signals φ2 and φ3 received from S/Hand comparators 2 and 3 to generate and output an internal data signalφ4 to decoder 5 and also generate and externally output digital codes DAand DB corresponding to analog input voltages VIA and VIB. Digital codesDA and DB each include a multibit (herein, 3-bit to simplify thedescription) data signal. Decoder 5 receives internal data signal φ4from SAR and control circuit 4 and decodes signal φ4 to generate andoutput a control signal φ5 to reference voltage generator 6.

With reference to FIG. 2, reference voltage generator 6 includes aresistor ladder 7 and a selector 9. Resistor ladder 7 includes aplurality of series connected resistor elements 8 to divide externallyapplied reference voltages for high and low reference voltages VRP andVRN, respectively, to generate nine levels of reference voltage V0–V8.Selector 9 receives control signal φ5 from decoder 5 and in accordancetherewith selects one of the nine levels of reference voltage V0–V8 toprovide the selected voltage as reference voltage VC to each of S/H andcomparators 2 and 3.

FIGS. 3A and 3B are timing plots for illustrating successiveapproximation A/D converter 1 in operation. As shown in the figures,successive approximation A/D converter 1 operates in response to arising edge of clock signal CLK on the basis of a period of one cycle(one period) of clock signal CLK.

To perform A/D conversion once, sampling S for a period of one cycle andcomparison C for a period of eight cycles are performed, and comparisonC includes S/H and comparator 2 performing comparison three times, i.e.,comparisons CA1–CA3, and SAR and control circuit 4 performing a latchLAA once, and S/H and comparator 3 performing comparison three times,i.e., comparisons CB1–CB3, and SAR and control circuit 4 performing alatch LAB once.

Initially in a cycle 1 (time t0 to time t1) S/H and comparators 2 and 3sample (S) external analog input voltages VIA and VIB. The sampledexternal analog input voltages VIA and VIB are held by S/H andcomparators 2 and 3, respectively, in response to clock signal CLKrising at time t1. The voltages held by S/H and comparators 2 and 3 willbe referred to as VHA and VHB, respectively.

In a cycle 2 (time t1 to time t2) reference voltage generator 6 setsreference voltage VC at reference voltage V4 intermediate between V0 andV8 and S/H and comparator 2 compares VHA with V4 (CA1). Herein, VHA is avoltage between V2 and V3 for the sake of illustration. VHA<V4, andsignal φ2 is set low (0).

In a cycle 3 (time t2 to time t3), in response to signal φ2 SAR andcontrol circuit 4, decoder 5 and reference voltage generator 6 setsreference voltage VC at voltage V2 between intermediate voltage V4 andlowest voltage V0 and S/H and comparator 2 compares VHA with V2 (CA2).VHA>V2, and signal φ2 set high (1).

In a cycle 4 (time t3 to time t4), in response to signal φ2 SAR andcontrol circuit 4, decoder 5 and reference voltage generator 6 sets 0reference voltage VC at voltage V3 between V2 and intermediate voltageV4 and S/H and comparator 2 compares VHA with V3 (CA3). VHA<V3, andsignal φ2 set low (0).

In a cycle 5 (time t4 to time t5) signals φ2 for four cycles 2–4 arelatched by SAR and control circuit 4 (LAA) and output as data codeDA(0)=010. Signal φ2 for cycle 2 serves as data code DA's MSB and signalφ2 for cycle 4 serves as data code DA's LSB. In cycle 5, referencevoltage generator 6 resets reference voltage VC to voltage V4intermediate between V0 and V8. Note that data code DA(0) is preceded bydata code DA(−1), which indicates a result of previous A/D conversion.

In a cycle 6 (time t5 to time t6) reference voltage generator 6 setsreference voltage VC at voltage V4 intermediate between V0 and V8 andS/H and comparator 3 compares VHB with V4 (CB1). Herein, VHB is avoltage between V5 and V6 for the sake of illustration. VHB>V4, andsignal φ3 is set high (1).

In a cycle 7 (time t6 to time t7), in response to signal φ3 SAR andcontrol circuit 4, decoder 5 and reference voltage generator 6 setsreference voltage VC at voltage V6 between intermediate voltage V4 andhighest voltage V8 and S/H and comparator 3 compares VHB with V6 (CB2).VHB<V6, and signal φ3 set low (0).

In a cycle 8 (time t7 to time t8), in response to signal φ3 SAR andcontrol circuit 4, decoder 5 and reference voltage generator 6 setsreference voltage VC at voltage V5 between V6 and V4 and S/H andcomparator 3 compares VHB with V5 (CB3). VHA>V5, and signal φ3 set high(1).

In a cycle 9 (time t8 to time t9) signals φ3 for four cycles 6–8 arelatched by SAR and control circuit 4 (LAB) and output as data codeDB(0)=101. Signal φ3 for cycle 6 serves as data code DB's MSB and signalφ3 for cycle 8 serves as data code DB's LSB. In cycle 9, referencevoltage generator 6 resets reference voltage VC to voltage V4intermediate between V0 and V8. Note that data code DB(0) is preceded bydata code DB(−1), which indicates a result of previous A/D conversion.

In the first embodiment two S/H and comparators 2 and 3 allow two analoginput voltages VIA and VIB to simultaneously be sampled. Furthermore,two S/H and comparators 2 and 3 sharing SAR and control circuit 4,decoder 5 and reference voltage generator 6 can contribute to a reducedchip area.

Note that while the first embodiment has been described in conjunctionwith a single-input and single-output, successive approximation A/Dconverter 1, the present invention is also applicable to differentialinput and differential output, successive approximation A/D converters.

Furthermore, while in the first embodiment two S/H and comparators 2 and3 share SAR and control circuit 4, decoder 5 and reference voltagegenerators 6, more than two S/H and comparators may share SAR andcontrol circuit 4, decoder 5 and reference voltage generator 6. Afurther effectively reduced chip area can be achieved.

Furthermore, as S/H and comparators 2 and 3 perform first comparisonsCA1 and CB2 using a single reference voltage VC=V4, S/H and comparators2 and 3 may perform the first comparisons CA1 and CB1 in the same cycle2, as shown in FIGS. 4A and 4B. In that case, the time required toperform A/D conversion once can be reduced by one cycle.

Second Embodiment

FIG. 5 is a block diagram showing a configuration of a successiveapproximation A/D converter 10 of the present invention in a secondembodiment. With reference to FIG. 5, successive approximation A/Dconverter 10 differs from the FIG. 1 successive approximation A/Dconverter 1 in that the former further includes a switch 11. Switch 11is controlled by SAR and control circuit 4. While S/H and comparator 3performs comparisons CB1–CB3, switch 11 passes S/H and comparator 3reference voltage VC generated by reference voltage generator 6. WhileS/H and comparator 3 does not perform comparisons CB1–CB3, switch 11passes S/H and comparator 3 voltage V4 used by S/H and comparator 3 forthe first comparison CB1.

In the FIG. 1 successive approximation A/D converter 1 S/H andcomparator 3 also compares VIB and VC in cycles 2–5 of FIGS. 3A and 3Band signal φ3 varies in level. If signal φ3 varies in level in cycles 5and 6, a recovery time is required for signal φ3 to vary in level. Thisrecovery time is, however, an obstacle to speeding up the successiveapproximation A/D converter and increasing its precision.

For successive approximation A/D converter 10, in cycles 2–5 V4 isapplied to S/H and comparator 3. Accordingly in cycles 5 and 6 signal φ3does not vary in level and recovery time is not introduced. Successiveapproximation A/D converter 10 can be operated faster and increased inprecision.

If S/H and comparator 3 does not perform comparisons CB1–CB3 referencevoltage generator 6 and S/H and comparator 3 may electrically bedisconnected, although in that case S/H and comparator 3 has acomparison voltage input node attaining high impedance state, and noiseor the like destabilizes signal φ3 in level and recovery time isintroduced.

Furthermore while the FIG. 5 successive approximation A/D converter 10employs intermediate voltage V4 generated in reference voltage generator6 at resistor ladder 7, intermediate voltage V4 may be generated by aseparately provided voltage divider circuit.

Third Embodiment

FIG. 6 is a circuit block diagram showing a configuration of asuccessive approximation A/D converter 20 of the present invention in athird embodiment. With reference to FIG. 6, successive approximation A/Dconverter 20 includes S/H and comparators 2 and 3, an SAR and controlcircuit 21, a decoder 21 and a reference voltage generator 23. S/H andcomparators 2 and 3 operate as has been described with reference to FIG.1.

SAR and control circuit 21 is synchronized with external clock signalCLK to operate to control S/H and comparators 2 and 3. Furthermore, SARand control circuit 21 is driven by signals φ2 and φ3 received from S/Hand comparators 2 and 3 and indicating resultant comparisons to generateand output internal data signals φ21A and φ21B to decoder 22 and alsogenerate and externally output digital codes DA and DB corresponding toanalog input voltages VIA and VIB.

Decoder 22 receives internal data signals φ21A and φ21B from SAR andcontrol circuit 21 and decodes them to generate and output a controlsignals φ22A and φ22B to reference voltage generator 23.

With reference to FIG. 7, reference voltage generator 23 includesresistor ladder 7 and selectors 24 and 25. Resistor ladder 7 isidentical to that shown in FIG. 2, dividing a voltage between referencevoltages VRP and VRN to generate nine levels of reference voltage V0–V8.Selector 24 operates in response to control signal φ22A received fromdecoder 22 to select one of the nine levels of reference voltage V0–V8and provide the selected voltage as a reference voltage VCA to S/H andcomparator 2. Selector 25 operates in response to control signal φ22Breceived from decoder 22 to select one of the nine levels of referencevoltage V0–V8 and provide the selected voltage as a reference voltageVCB to S/H and comparator 3.

FIGS. 8A and 8B are timing plots for illustrating successiveapproximation A/D converter 20 in operation. As shown in the figures,successive approximation A/D converter 20 operates in response to arising edge of clock signal CLK on the basis of a period of one cycle ofclock signal CLK.

To perform A/D conversion once, sampling S for a period of one cycle andcomparison C for a period of four cycles are performed, and comparison Cincludes S/H and comparator 2 performing comparison three times, i.e.,comparisons CA1–CA3, and SAR and control circuit 21 performing latch LAAonce, and S/H and comparator 3 performing comparison three times, i.e.,comparisons CB1–CB3, and SAR and control circuit 21 performing latch LABonce. Comparisons CA1–CA3 and latch LAA, and comparisons CB1–CB3 andlatch LAB are performed in parallel.

Initially in cycle 1 (time t0 to time t1) S/H and comparators 2 and 3sample external analog input voltages VIA and VIB. The sampled externalanalog input voltages VIA and VIB are held by S/H and comparators 2 and3, respectively, in response to clock signal CLK rising at time t1. Thevoltages held by S/H and comparators 2 and 3 will be referred to as VHAand VHB, respectively.

In cycle 2 (time t1 to time t2) reference voltage generator 23 setsreference voltages VCA and VCB both at voltage V4 and S/H and comparator2 compares VHA with V4 (CA1) and S/H and comparator 3 compares VHB withV4 (CB1). Herein, V2<VHA<V3 and V5<VHB<V6 for the sake of illustration.VHA<V4 and VHB>V4, and signals φ2 and φ3 are set low (0) and high (1),respectively.

In cycle 3 (time t2 to time t3), in response to signals φ2 and φ3reference voltage generator 23 sets reference voltages VCA and VCB atvoltages V2 and V6, respectively, and S/H and comparator 2 compares VHAwith V2 (CA2) and S/H and comparator 3 compares VHB with V6 (CB2).VHA>V2 and VHB<V6, and signals φ2 and φ3 are set high (1) and low (0),respectively.

In cycle 4 (time t3 to time t4), in response to signals φ2 and φ3reference voltage generator 23 sets reference voltages VCA and VCB atvoltages V3 and V5, respectively, and S/H and comparator 2 compares VHAwith V3 (CA3) and S/H and comparator 3 compares VHB with V5 (CB3).VHA<V3 and VHB>V5, and signals φ2 and φ3 are set low (0) and high (1),respectively.

In cycle 5 (time t4 to time t5) signals φ2 and φ3 for four cycles 2–4are latched by SAR and control circuit 4 (LAA and LAB) and output asdata codes DA(0)=010 and DB(0)=101. Signals 42 and φ3 for cycle 2 serveas data code DA's MSB and data code DB's MSB, respectively, and signalsφ2 and φ3 for cycle 4 serve as data code DA's LSB and data code DB'sLSB, respectively. Note that data codes DA(0) and DB(0) are preceded bydata codes DA(−1) and DB(−1), which indicate a result of previous A/Dconversion.

The third embodiment allows sampling, comparison and latching to beperformed for two analog input voltages VIA and VIB in parallel. Thiscan reduce the number of cycles required to perform A/D conversion onceas compared with the first and second embodiments. Furthermore, two S/Hand comparators 2 and 3 sharing resistor ladder 7 can contribute to areduced chip area.

FIG. 9 is a circuit block diagram showing the third embodiment in anexemplary variation. With reference to the figure, this successiveapproximation A/D converter does not employ reference voltage generator23 of FIG. 7 and instead employs a reference voltage generator 30.Reference voltage generator 30 corresponds to reference voltagegenerator 23 with resistor ladder 7 replaced with an intermesh resistorladder 31 including eight resistor elements 8 connected in seriesbetween a node for a reference voltage for higher voltage VRP and a nodefor a reference voltage for lower voltage VRN, and two intermeshresistor elements 32, one connected between nodes for V8 and V4, and theother between those for V0 and V4. The exemplary variation introducingintermesh resistor elements 32 allows reference voltage generator 30 tohave an increased capability to supply a current to allow referencevoltages VCA and VCB to vary in level faster so that the successiveapproximation A/D converter can operate rapidly and be increased inprecision. Note that while in this exemplary variation every fourresistor elements are associated with a single intermesh resistorelement 32 connected in parallel therewith, every two resistor elements8 may be associated with a single intermesh resistor element 32connected in parallel therewith.

Although the present invention has been described and illustrated indetail, it is clearly understood that the same is by way of illustrationand example only and is not to be taken by way of limitation, the spiritand scope of the present invention being limited only by the terms ofthe appended claims.

1. A successive approximation A/D converter comprising: a first analoginput terminal for receiving a first analog signal; a second analoginput terminal for receiving a second analog signal; a first comparatorcoupled to said first analog input terminal; a second comparator coupledto said second analog input terminal; and a control circuit forselecting said first comparator to generate a first digital code andselecting said second comparator to generate a second digital codesequentially; wherein said first analog input signal is applied only tosaid first comparator and said second analog input signal is appliedonly to said second comparator for generation, respectively, of thefirst and second digital codes.
 2. The successive approximation A/Dconverter of claim 1, wherein said control circuit is synchronized witha clock signal to operate to control said first and second comparators.3. The successive approximation A/D converter of claim 1, wherein saidcontrol circuit latches said first digital code before selecting saidsecond comparator.
 4. The successive approximation A/D of claim 1,further comprising: a first sample and hold circuit coupled to saidfirst comparator; and a second sample and hold circuit coupled to saidsecond comparator.